1. Field of the Invention
The invention relates generally to the testing of electronic circuits, and more particularly to systems and methods for increasing the number of devices having LBIST circuitry that can be tested at the same time by reducing the number of necessary connections between the devices under test and a test system.
2. Related Art
Digital devices are becoming increasingly complex. As the complexity of these devices increases, there are more and more chances for defects that may impair or impede proper operation of the devices. The testing of these devices is therefore becoming increasingly important.
Testing of a device may be important at various stages, including in the design of the device, in the manufacturing of the device, and in the operation of the device. Testing at the design stage ensures that the design is conceptually sound. Testing during the manufacturing stage may be performed to ensure that the timing, proper operation and performance of the device are as expected. Finally, after the device is manufactured, it may be necessary to test the device at normal operating speeds to ensure that it continues to operate properly during normal usage.
One way to test for defects in a logic circuit is to deterministic approach. In a deterministic method, each possible input pattern is applied at the inputs of the logic circuit, with each possible set of state values in the circuit. The output pattern generated by each set of inputs and state values is then compared with the expected output pattern to determine whether the logic circuit operated properly. If the number of possible input patterns and state values is high, however, the cost of deterministic testing of all the combinations is generally too high for this methodology to be practical. An alternative method of testing that has a lower cost is therefore desirable.
One alternative is a non-deterministic approach in which pseudorandom input test patterns are applied to the inputs of the logic circuit. The outputs of the logic circuit are then compared to the outputs generated in response to the same pseudorandom input test patterns by a logic circuit that is known to operate properly. If the outputs are the same, there is a high probability that the logic circuit being tested also operates properly. The more input test patterns that are applied to the logic circuits, and the more random the input test patterns, the greater the probability that the logic circuit under test will operate properly in response to any given input pattern. This non-deterministic testing approach is typically easier and less expensive to implement than a deterministic approach.
One test mechanism that can be used to implement a deterministic testing approach is a built-in self test (BIST). This may also be referred to as a logic built-in self test (LBIST) when applied to logic circuits. BIST and LBIST methodologies are generally considered part of a group of methodologies referred to as design-for-test (DFT) methodologies. DFT methodologies impact the actual designs of the circuits that are to be tested. LBIST methodologies in particular involve incorporating circuit components into the design of the circuit to be tested, where the additional circuit components are used for purposes of testing the operation of the circuit's logic gates.
In a typical LBIST system, LBIST circuitry within a device under test includes a plurality of scan chains interposed between levels of the functional logic of the device. The automated test equipment or the LBIST circuitry provides input bit patterns that are scanned into the scan chains and then propagated through the functional logic to subsequent scan chains. The computed bits (the bits that are propagated through the functional logic) are then scanned out of the scan chains into a multiple-input signature register (MISR,) where the computed bits from the scan chains are combined into a test signature. The size of the signature is equal to one bit for each of the scan chains). This test cycle is typically repeated many times (e.g., 10,000 iterations,) with the results of each test cycle being combined in some manner with the results of the previous test cycles. After all of the scheduled test cycles have been completed, the final result (the test signature) is passed back to the automated test equipment to be compared to a final result generated by a device that is know to operate properly. Based on this comparison, it is determined whether the device under test operates properly.
This conventional configuration has some drawbacks, however. Each of the devices requires a number of connections for support such as power and control signals, for input such as the test patterns, and for output such as the computed test results. The total number of connections not only scales with the number of devices but, as in the case of the device output, with the number of scan chains within the LBIST circuitry.
It is typically desirable to be able to test multiple integrated circuits at the same time on a single test system. The test system can normally make a limited number of connections to the integrated circuits under test. Because of the large number of pins that may be required for each device, however, the number of devices that can be tested at a single time may be severely limited.
It would therefore be desirable to provide systems and methods for decreasing the number of pins/connections required by each of the devices, thereby increasing the number of devices that can be coupled to a test system for performing LBIST testing on the devices.